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首页> 外文期刊>IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences >A 0.3-V Operating, V_(th)-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond
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A 0.3-V Operating, V_(th)-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

机译:在90纳米技术时代及以后的DVS环境下,适用于内存丰富的SoC的0.3V工作,V_(th)变化容限SRAM

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摘要

We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy word-line and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30% can be achieved at 100 MHz. In a 65-nm 64-Mb SRAM, a 74% power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1%, and area overhead is 5.6%.
机译:我们提出了一种用于6T SRAM单元的电压控制方案,该方案可在DVS环境下将最低工作电压降至0.3V。根据读取和写入操作来控制向存储单元和字线驱动器提供的电源电压,位线电压和负载pMOSFET的体偏置电压,即使在低工作电压下也能确保工作裕度。还引入了具有伪字线及其反馈的自对准时序控制,以确保在很宽的电源电压范围内稳定运行。在90纳米工艺技术中对64 kb SRAM的测量结果表明,在100 MHz时可以实现30%的功耗降低。在65nm 64-Mb SRAM中,预计最大工作频率的1/6可以节省74%的功率。所提出的方案的性能损失小于1%,并且面积开销为5.6%。

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