机译:基于单序列表示的具有边界约束的VLSI布局
School of Electronic Engineering, University of Electronic Science and Technology of China, Chengdu, 610054, China;
School of Electronic Engineering, University of Electronic Science and Technology of China, Chengdu, 610054, China;
School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu, 610054, China;
VLSI physical design; floorplan/placement; boundary constraints; single-sequence;
机译:使用角块列表表示法具有边界约束的VLSI布局规划
机译:基于B * -Tree表示的非切片VLSI平面规划的新型高速模拟退火算法
机译:聚类约束的VLSI布局的蚁群优化
机译:基于角块列表的具有边界约束的VLSI布局规划
机译:VLSI设计的方法和基于约束的布局语言(分层设计)
机译:变形建模使用3D边界表示与百隆骨架的分支结构二次约束
机译:VLSI布局规划中的非切片布局规划表示形式:摘要