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机译:基于标准单元的CMOS数字电路中电源噪声产生的建模
Department of Computer and Systems Engineering, Kobe University, Kobe-shi, 657-8501 Japan;
Department of Computer and Systems Engineering, Kobe University, Kobe-shi, 657-8501 Japan;
Department of Computer and Systems Engineering, Kobe University, Kobe-shi, 657-8501 Japan JST, CREST;
substrate noise; power supply noise; signal integrity; substrate coupling; power integrity;
机译:模拟CMOS数字集成电路中基板噪声的产生
机译:模拟CMOS数字集成电路中基板噪声的产生
机译:CMOS数字集成电路中的衬底噪声产生
机译:模拟CMOS数字集成电路中基板噪声的产生
机译:使用分段线性模型对CMOS数字电路进行功率建模。
机译:用于超低噪声CMOS图像传感器的基于多采样的信号读取电路的降噪效果
机译:高压低功耗CMOS模拟电路,用于高斯和均匀的噪音