Jitter Amplifier for Oscillator-Based True Random Number Generator

摘要

We propose a jitter amplifier architecture for an oscillatorbased true random number generator (TRNG). Two types of latencycontrollable (LC) buffer, which are the key components of the proposed jitter amplifier, are presented. We derive an equation to estimate the gain of the jitter amplifier, and analyze sufficient conditions for the proposed circuit to work properly. The proposed jitter amplifier was fabricated with a 65 nm CMOS process. The jitter amplifier with the two-voltage LC buffer occupied 3,300 μm~2 and attained 8.4x gain, and that with the single-voltage LC buffer achieved 2.2x gain with an 1,700/μm~2 area. The jitter amplification of the sampling clock increased the entropy of a bit stream and improved the results of the NIST test suite so that all the tests passed whereas TRNGs with simple correctors failed. The jitter amplifier attained higher throughput per area than a frequency divider when the required amount of jitter was more than two times larger than the inherent jitter in our test-chip implementations.