Circuit-Simulation Model of C_(gd) Changes in Small-Size MOSFETs Due to High Channel-Field Gradients

摘要

Small-size MOSFETs are becoming core devices in RF applications because of improved high frequency characteristics. For reliable design of RF integrated circuits operating at the GHz range, accurate modeling of small-size MOSFET characteristics is indispensable. In MOSFETs with reduced gate length (L_g), the lateral field along the MOSFET channel is becoming more pronounced, causing short-channel effects. These effects should be included in the device modeling used for circuit simulation. In this work, we investigated the effects of the field gradient in the gate-drain capacitance (C_(gd). 2-Dimensional (2D) simulations done with MEDICI show that the field gradient, as it influences the channel condition, induces a capacitance which is visible in the MOSFET saturation operation. Changes in C_(gd) is incorporated in the modeling by an induced capacitance approach. The new approach has been successfully implemented in the surface-potential based model HiSIM (Hiroshima-university STARC IGFET Model) and is capable of reproducing accurately the measured C_(gd)-L_g characteristics, which are particularly significant for pocket-implant technology. Results show that pocket-implantation introduces a steep potential increase near the drain region, which results to a shift of the C_(gd) transition region (from linear to saturation) to lower bias voltages. C_(gd) at saturation decreases with L_g due to steeper surface potential and increased impurity concentration effects at reduced L_g.