A Chip Set for Programmable Real-Time MPEG2 MP @ ML Video Encoder

摘要

This paper describes a chip set architecture and its implementation for programmable MPEG2 MP @ ML (main profile at man level) video encoder. The chip set features a functional partitioning architecture based on the MPEG2 layer structure. Using this partitioning scheme, an optimized system configuration with double bus structure is propose. In addi- tion, a hybrid architecture with dual video-oriented on-chip RISC processors and dedicated hardware and a hierarchical pipeline scheme covering all layers are newly introduced to realize flexibility.