CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes

摘要

The charge-redistribution low-swing differential logic (CLDL) circuits are presented in this work. It can implement a com plex function in a single gate. The CLDL circuits utilizes the charge redistribution and reduced-swing schemes to reduce the power dissipation and enhance the operation speed. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. The CLDL circuits perform more than 25% speedup and 31% in power-delay product compared to other differential circuits with true-single-phase clock. A pipelined multiplier accumulator (MAC) using CLDL structure is fabricated in 0.35 μm single poly four-metal CMOS process. The test chip is successfully verified to operate at 900-MHz.