The author proposed a hybrid method as ESD estimation technique at design stage. It consists of a conducted immunity measurement and a circuit analysis. The hybrid method was applied to the immunity of the printed circuit boards with ICs, and the results of our simulation were verified experimentally. First, The conducted noise generated by ESD-gun injected the IC gate ,and the voltage was measured at IC gate when the IC malfunction. Next, the capacitance between layers of the print circuit board is calculated by the static electricity field analysis. The equivalent circuit is constructed with the capacitance of the printed circuit board and the ESD-gun. The equivalent circuit was analyzed by the circuit analysis, and the voltage induced between the power supply layer and the ground layer of the print circuit board was calculated. Finally, the ESD-gun output that the print circuit board mounted the IC malfunctions was calculated from these results. The results of our simulation were verified experimentally.%本稿では，設計段階で適用できるESD評価手法として，ICの伝導イミュニティ特性測定と回路解析を連携した解析手法を提案し，ICを実装したプリント回路基板のイミュニティ評価に適用して，実測で検証した．1Cの伝導イミュニティ特性測定では，ESDガンの出力を伝導ノイズにしてIC端子（電源－グラウンド間）に印加することにより，lCが誤動作する入力電圧を測定した．また回路解析により，ESDガンとプリント回路基板から構成される等価回路を解析し，IC端子に誘起する電圧を算出した．これらの結果であるIC誤動作時のIC端の入力電圧と，IC端子の誘起電圧の比から，プリント回路基板に実装したICが誤動作するESDガン出力を算出した．実測により，本連携解析から得られた解析結果を検証して，妥当であることを示した．
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