A 0.18 μm CMOS over 10 Gb/s 10-PAM Serial Link Receiver

摘要

A multi Gb/s multi-level pulse amplitude modulation (PAM) receiver for chip to chip communication is proposed. Increasing data bit rate is achieved with 10-PAM. To increase data bit-rate and reduce BER, We designed this circuit by using a current mode amplifier, CML circuit. The 10-PAM receiver is designed in 0.18 μm CMOS technology and achieves Gb/s of data bit rates. The simulated BER is less than 1.0×10~(-12). The simulation results showed that the 0.5 × 0.6 mm~2 chip consumes 57 mA at 12.8 Gb/s from a 1.8-V supply.