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SAT and SMT Based Model Checking of Concurrent Systems

机译:基于SAT和SMT的并发系统模型检查。

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We discuss model checking that uses a SAT (satisfiability) or SMT (satisfiability modulo theory) solver. The basic idea behind this model checking approach is to reduce the model checking problem to the satisfiability problem of a formula of some logic. Recent advances in SAT and SMT solvers make this particular approach sig-nificantly attractive. However, it does not work effectively in verification of concurrent systems, because the size of the formula blows up if the system has high concurrency. To overcome this challenge, we propose a new semantics for concurrent systems. The new semantics allows a compact formula representation of the behavior of concurrent systems. In this paper, we first introduce this new semantics and bounded model checking based on it, in the context of a general model of concurrent systems. Then we apply it to two specific concurrent system models, namely Petri nets and concurrent programs using unbounded integer variables.
机译:我们讨论使用SAT(可满足性)或SMT(可满足性模理论)求解器的模型检查。这种模型检查方法的基本思想是将模型检查问题简化为某种逻辑公式的可满足性问题。 SAT和SMT求解器的最新进展使这种特殊方法具有极大的吸引力。但是,它在并发系统的验证中不能有效地工作,因为如果系统具有高并发性,则公式的大小会膨胀。为了克服这一挑战,我们为并发系统提出了一种新的语义。新的语义允许对并发系统的行为进行紧凑的公式表示。在本文中,我们首先在并发系统的通用模型的背景下介绍这种新的语义和基于它的边界模型检查。然后,将其应用于两个特定的并发系统模型,即Petri网和使用无界整数变量的并发程序。

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