An FPGA Implementation of CRC Slicing-by-N algorithms

摘要

Cyclic Redundancy Check (CRC) is an error detection scheme that detects corruption of digital content during data transmission, processing or storage. The process of calculating the CRC values of a large amounts of data is most computationally intensive process when processing a protocol. The proposed software solutions are not able to generate CRC values at a very high speed (10 Gbps or higher), due to the limitations of current speed of processors. This paper examines new computer architectures for accelerating the process of calculating CRC using programmable logic - FPGA. Our hardware implementation was based on a newly proposed "Slicing-by-N" CRC algorithms that are using multiple tables and reading 32, 64, 128 and 256 bits at a time. We examine achievable clock speed, throughput and area utilization.