Soft Error-Aware Scheduling in High-Level Synthesis

摘要

Due to the continuous reduction in chip feature size and supply voltage, soft errors are becoming a serious problem in the today's LSI design. This paper proposes a soft error-aware scheduling method in high-level synthesis. The reliability of the datapath circuit is determined not only by those of its computations, which depend on their assigned hardware resources, but also by those of its values, which are affected by their lifetime length. By considering both influences, our proposed method schedules operations for maximizing the reliability of the datapath circuit.