Via数削減による大規模LSIレイアウトの高速DRC手法

摘要

GDSⅡなどのレイアウトデータでは，多層配線の配線間の接続箇所にViaが使用されているが，近年，DFM（Design for Manufacturability）技術の浸透により，配置されるViaの数が爆発的に増加している.Via図形のデータが増加すると，DRC（Design Rule Check）を行うEDAツールにとっては，計算コストが増大し，解析に多くの時間とメモリ空間を必要とする.そこで本研究では，解析データからViaを必要最小限まで擬似的に削減し，その上でDRCの一つである配線幅チェックを行った.Viaを削減しない場合と比較して，数倍～数百倍解析時間が短縮された.%In layout data such as GDS II, Vias are used for connection points between multilayer wiring. In recent years, the number of Vias to be arranged has been increasing explosively in accordance with the spread of DFM (Design for Manufacturability) technology. Increase of Via graphic data would rise computation costs for an EDA tool that performs DRC (Design Rule Check) and require long time and memory space for an analysis. Therefore, in this study, Vias were spuriously reduced to minimum from analysis data and the wire width was checked, which was one of the DRCs. Comparing with the case that Vias are not reduced, analysis time has been shortened by several times - several hundred times.