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首页> 外文期刊>電子情報通信学会技術研究報告 >A Low-Jitter 1.5-GHz and Large-EMI reduction 10-dBm Spread-Spectrum Clock Generator for Serial-ATA
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A Low-Jitter 1.5-GHz and Large-EMI reduction 10-dBm Spread-Spectrum Clock Generator for Serial-ATA

机译:用于串行ATA的低抖动1.5GHz和大EMI降低10dBm扩频时钟发生器

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摘要

A low-jitter and large-EMI-reduction spread spectrum clock generator (SSCG) for Serial-ATA (SATA) was developed. A low-jitter voltage-controlled oscillator (VCO) with a high-frequency limiter was developed to prevent the SSCG from malfunctioning. This VCO achieved far less jitter than that of a conventional VCO. An auto-calibration technique suitable for this VCO was developed to prevent the SSCG from degrading performance because of process variations. A SATA-PHY using a technique for calibrating the SSCG was developed to use an inexpensive but large frequency-variation reference oscillator. This technique was used to calibrate the SSCG output-signal frequency. This is achieved by shifting an SSCG divide ratio by utilizing the difference between an SSCG output signal frequency and a received signal frequency. These techniques were fabricated in 0.13- and 0.15-μm CMOS processes. The proposed SSCG achieved a 10.0-dB reduction in EMI. The variation in the rms jitter at 1.5 GHz with spread-spectrum clocking was reduced from 2.1-7.8 ps to 1.9-3.3 ps by the proposed autocalibration technique. The proposed SATA PHY achieved less than 400-ppm production-frequency tolerance of reference clocks.
机译:开发了用于串行ATA(SATA)的低抖动,大幅度降低EMI的扩频时钟发生器(SSCG)。为了防止SSCG发生故障,开发了带有高频限制器的低抖动压控振荡器(VCO)。该VCO的抖动远低于常规VCO。开发了一种适用于该VCO的自动校准技术,以防止SSCG由于工艺变化而降低性能。已开发出一种使用用于校准SSCG的技术的SATA-PHY,以使用廉价但频率变化较大的参考振荡器。该技术用于校准SSCG输出信号频率。这是通过利用SSCG输出信号频率和接收信号频率之间的差来移动SSCG分频比来实现的。这些技术是在0.13和0.15μmCMOS工艺中制造的。拟议的SSCG可以将EMI降低10.0 dB。通过提议的自动校准技术,扩展频谱时钟在1.5 GHz时均方根抖动的变化从2.1-7.8 ps降低到1.9-3.3 ps。拟议的SATA PHY实现了低于400 ppm的参考时钟生产频率容限。

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