Power Efficient Design of Arithmetic Circuits Based on Embedded Memory Blocks in FPGA

摘要

Current generation FPGAs provide a large number of embedded memory blocks which can be used to create single or dual port RAM, ROM and FIFOs, and able to be configured in many different width and depth combinations. Some part of the unutilized memory blocks can be used to implement logic circuits, to unburden the routing resources. The objective of our research is to reduce power by using the embedded memory blocks in FPGAs. The basic method is applied to arithmetic circuits such as 8-bit counter, 4-bit adder and 4-bit multiplier. They consume less power when mapped into EMBs compared with traditional mapping method. The power reduction is 23% on Stratix device family. Since the memory resources in FPGA are limited, the memory size reduction methods based on the decomposition and the re-formulation have been shown. Experimental results show that there might exist the trade-off between the memory size and the power consumption.