The COB stack DRAM cell at technology node below 100 nm-scalingissues and directions

摘要

The scaling of the 8F2 COB stack DRAM cell down ton70-nm technology node is described. Issues and possible solutionsnregarding critical points, such as the difficulty in achievingnsufficient memory cell capacitance, degraded cell transistornperformance, and increased junction leakage current at storage node areninvestigated. Although its unit cell size is bigger than those of opennbit line cell architectures, the 8F2 COB stack cell can benthe most suitable technology for 70-mn DRAM technology node due to itsnexcellent noise immunity and large capacitor area