Multilayer and Multiproduct Masks: Cost Reduction Methodology

摘要

The cost of reticles is growing twice as fast as the overall cost of new process development for technologies beyond the 100-nm node [1], [2]. In order for the integrated circuit design to continuously benefit from the shrinkpath in alignment with Moore's law [3], the industry should explore cost-effective approaches for the mask data [(intellectual property (IP)] placement alternative to the standard methodology of one mask for one layer of one product [4]. The implementation of multi-IP placements, using multilayer or multiproduct (shuttle) masks, is based on complex technical and economical analysis to maximize mask return on investment (ROI) over the product lifetime. The key criteria include the ability to match layers or products on one plate with respect to the CD control and pattern density and the expected time or fab volume prior to the conversion to the dedicated mask set for successful products. This work analyzes the links between the IP content of the mask, the product market price, and the wafer volume. As an example, by taking into account the cost of the exposure and of the mask, one can show that for 100-nm technology, positive ROI would be achieved for a product or test vehicle with volume depending on the architecture of the multilayer mask set. We compare the key challenges of the two basic multi-IP mask approaches, the multilayer and the multiproduct masks, and discuss the best conditions for their implementation. Directions for future research are also proposed.