Pulsewidth Modulations for the Comprehensive Capacitor Voltage Balance of $n$-Level Two-Leg Diode-Clamped Converters

摘要

This paper presents the definition of the virtual vectors for the general case of an n-level two-leg diode-clamped converter, suggests guidelines for designing virtual-vector pulsewidth modulation (PWM) strategies, and provides the mathematical expressions of the leg duty-ratio waveforms corresponding to this family of PWMs. Modulations defined upon these vectors guarantee the dc-link capacitor voltage balance in every switching cycle under any type of load and enable the use of these topologies with passive front ends. The performance of these multilevel converters operated with the proposed PWMs is compared to the performance of alternative designs through analysis, simulation, and experiments.