Digital Controller for DVS-Enabled DC–DC Converter

摘要

A high-frequency digital controller that includes an optimized analog-digital converter (ADC) with a novel formulation of digital error value based on target clock frequency and converter output voltage is presented in this paper. A programmable look-up table-based digital compensator is implemented for fast processing the feedback error. Limitations of a hybrid digital pulsewidth modulator (DPWM) at high frequency are addressed and solved by an edge-triggered logic. Support for process, voltage, and temperature variations is incorporated in the integrated design. Target clock frequency denotes the frequency of the signal which is driven by dynamic voltage scaling (DVS) processor and corresponds to the reference value of the regulated output voltage. This work realizes the classical digital controller design implementation of a target frequency to minimum required regulated voltage for DVS-enabled adaptive DC-DC converter. A synchronous buck converter of 1 MHz switching frequency and the proposed delay-line-based optimized ADC have been fabricated for realizing and verifying the complete digital controller on a field-programmable gate array-based closed-loop prototype. Experimental results are presented, which demonstrate the fast dynamic response achieved for target clock frequency in the range of 6-16 MHz, corresponding to the regulated output voltage range of 1.6-3.2 V. The complete design of digital controller has been implemented in 0.5 ¿m CMOS technology using Cadence and Synopsys tools. The active on-chip area of the proposed delay-line ADC, digital compensator, and edge-triggered hybrid DPWM are 0.08, 0.28, and 0.07 mm2 respectively.