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Effect of Asymmetric Layout and Unequal Junction Temperature on Current Sharing of Paralleled SiC MOSFETs With Kelvin-Source Connection

机译:非对称布局和不等结温对与开尔文源连接相平行SiC MOSFET的电流共享的影响

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摘要

Parallel connection of silicon carbide (SiC) MOSFETs is a popular solution for high-capacity applications. In order to improve the switching speed of paralleled SiC MOSFETs, Kelvin-source connection is widely employed. However, the influences of asymmetric layout and unequal junction temperature on current sharing of paralleled SiC MOSFETs with Kelvin-source connection are not clear. This article addresses the issue for the first time by theoretical analysis and experimental verifications. The mechanism of current imbalance resulting from asymmetric layout and unequal junction temperature in the case with Kelvin-source connection is comprehensively investigated. Then, some significant discoveries are obtained. The static current sharing performance can be affected by drain and power source parasitic inductance, which is seldom mentioned before. Besides, this article first points out that the effect of power source parasitic inductance on dynamic current sharing is dominant compared with other parasitic inductance. What is more, the thermal-electric analyzing results suggest that there is a risk of thermal runaway for paralleled SiC MOSFETs with Kelvin-source connection at high switching frequency due to positively temperature-dependent dynamic current and switching losses. Based on the discoveries, some guidelines are provided for layout design and application of paralleled SiC MOSFETs with Kelvin-source connection.
机译:碳化硅(SiC)MOSFET的并联连接是高容量应用的流行解决方案。为了提高并联SiC MOSFET的开关速度,广泛采用Kelvin源连接。然而,不对称布局和不平等结温对具有克尔文源连接的并联SiC MOSFET电流共享的影响尚不清楚。本文首次通过理论分析和实验验证来解决此问题。综合研究了由kelvin源连接的不对称布局和不等结温产生的电流不平衡的机理。然后,获得了一些重要的发现。静态电流共享性能可能受到漏极和电源寄生电感的影响,以前很少提到。此外,本文首先指出,与其他寄生电感相比,电源寄生电感对动态电流共享的影响是显着的。更重要的是,热电分析结果表明,由于温度相关的动态电流和开关损耗,在高开关频率下具有Kelvin源连接的并联SiC MOSFET的热失控风险。基于发现,提供了一些指南,用于布局设计和应用与开尔文源连接的并联SIC MOSFET。

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