Analysis of the Steady-State Current Ripple in Multileg Class-D Power Amplifiers Under Inductance Mismatches

摘要

Multileg Class-D amplifiers (CDAs) with phase-shifted carrier modulation can increase the equivalent switching frequency and reduce the output current ripples, which further reduces the size of the output filter. However, these benefits are degraded by the tolerances in the phase inductance values. The phase inductance mismatches impact the ripple cancelation effects (the harmonic contents at switching frequency and its harmonics appearing in the output current ripple). Therefore, the quality of the output waveform can further be impacted. Current research works dealing with this issue mainly focused on the interleaved dc-dc converters, which does not cover the analysis in multileg CDAs or inverters, especially for the full-bridge configuration. This paper proposes a general analytical method to characterize the steady-state phase and the total current ripple in the multileg CDAs with full-bridge configuration under inductance mismatches. Monte Carlo simulation is used to study the impact of inductance mismatches on the harmonic contents of the total current ripple, and the distribution law of the inductances at the worst case is revealed. The analytical method is verified by simulation and experimental results of a four-leg full-bridge CDA. A design guideline is given to optimize the filter design based on the analytical method.