Design of Time-to-Digital Converters for Time-Over-Threshold Measurement in Picosecond Timing Detectors

摘要

In picosecond timing detectors, the time over threshold (TOT) of detector signals is normally required to be measured to enhance the front-edge timing precision. The extremely narrow pulsewidth of these detector signals has posed challenges to the design of time-to-digital converters (TDCs) based on field programmable gate arrays (FPGAs) for TOT measurement. In this article, an FPGA-based tapped-delay-line (TDL)-type TDC is proposed to simultaneously measure the arrival time and TOT time of nuclear pulses. By propagating the hit signal along a single TDL, the proposed bubble-proof encoding scheme can extract the time information of two transitions of hit signal in one measurement. The minimum measurable TOT time is proved to be limited only by the electrical characteristics of low-voltage differential signaling (LVDS) receivers of FPGAs. Through the performance evaluation on the prototype with a Virtex Ultrascale + FPGA, where the minimum measurable TOT time can be as low as 370 ps, the rms precision reaches 3.0 ps for TOT time measurement. Given the pulsewidths ranging from 0.4 to 1.5 ns, the measured TOT time is highly consistent with the direct readout values from the oscilloscope in a wide temperature range. To apply the TDC into a microchannel plate photomultiplier tube (MCP-PMT)-based timing detector, the front-end electronics board with a dual-threshold TOT measurement is constructed. The joint beam test results show that the coincidence time resolution of two identical detector channels can be improved from 36.5 to 10.3 ps, which demonstrates the significance of TOT measurement to modern picosecond timing detectors.