Design Consideration of Bulk FinFETs Devices With $hbox{rm n}^{+}hbox{/}^{}hbox{rm p}^{+}hbox{/}^{}hbox{rm n}^{{+}}$ Gate and $hbox{rm p}^{+}hbox{/}^{}hbox{rm n}^{{+}}

摘要

In this paper, design considerations for the $hbox{rm n}^{+}hbox{/}^{}hbox{rm p}^{+}hbox{/}^{}hbox{rm n}^{{+}}$ gate bulk FinFET in sub-50-nm technology nodes is extensively studied through 3-D device simulation. For the comparison of electrical characteristics of $hbox{rm n}^{+}hbox{/}^{}hbox{rm p}^{+}hbox{/}^{}hbox{rm n}^{{+}}$ gate bulk FinFET, the electrical characteristics of $hbox{rm p}^{+}hbox{/}hbox{rm n}^{+}$ gate bulk FinFET were also studied. The electrical characteristics of devices with different $hbox{rm n}^{+}$ gate lengths ($L_{rm s}$) and fin body widths ( $W_{{rm fin}}$) were compared in terms of threshold voltage ( $V_{{rm th}}$), on -current ($I_{{rm ON}}$), off -state current ($I_{{rm OFF}}$), subthreshold swing (SS), and drain-induced barrier lowering (DIBL). In this study, with a limit of gate length ( $L_{rm g} leq 50$ nm) and a fin body width ( $W_{rm fin} leq 30$ nm), bulk FinFETs were designed to achieve an off-current less than 1 fA. Two-nanometer-thick ${rm SiO}_{2}$ layers were inserted between an $hbox{rm n}^{+}$ gate and a $hbox{rm p}^{+}$ gate of the device with- $hbox{rm n}^{+}hbox{/}^{}hbox{rm p}^{+}hbox{/}^{}hbox{rm n}^{{+}}$ gate. Then, the electrical characteristics of the device were studied. Specifically, the source/drain to gate overlap length $(L_{rm ov}){rm s}$ were changed for both the bulk FinFETs with $hbox{rm n}^{+}hbox{/}^{}hbox{rm p}^{+}hbox{/}^{}hbox{rm n}^{{+}}$ gate and the device with a $hbox{rm p}^{+}$ gate. Then, the electrical characteristics of both devices were compared.