High-Efficiency LDMOS Power-Amplifier Design at 1 GHz Using an Optimized Transistor Model

摘要

A 10-W LDMOS harmonically tuned power amplifier at 1 GHz with state-of-the-art power-added efficiency of 80% is presented. The fundamental and second-harmonic load impedances are optimized for maximum efficiency while other harmonics are blocked by a low-pass load network. A simplified model of the transistor specialized for harmonically tuned and switched mode operations is proposed and used for the design. Good agreement between simulations and measurements is observed, indicating high accuracy of the model and design approach for these particular applications.