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Enhancement of Frequency Synthesizer Operating Range Using a Novel Frequency-Offset Technique for LTE-A and CR Applications

机译:使用新型频偏技术增强LTE-A和CR应用的频率合成器工作范围

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This paper presents a novel frequency-offset technique to enhance operating range of frequency synthesizers for long-term evolution-advanced and cognitive-radio applications. Conventional wideband frequency synthesizers typically have complex architectures, such as multiple phase-locked loops (PLLs), multiple voltage-controlled oscillators, and multiple mixers, to increase operating range. These complex architectures have high cost and power consumption. In this study, the proposed technique substantially increases the operating range of the frequency synthesizer by using only a single PLL to simultaneously lock two mixing oscillators. The presented frequency synthesizer is implemented using ${hbox {0.18-}}mu{hbox {m}}$ CMOS technology. Performance tests demonstrate that the frequency synthesizer achieves a very wide operating frequency range from 50 MHz to 4.8 GHz with a phase noise lower than $-{{hbox {100 dBc/Hz}}}$ at a frequency offset of 100 kHz. The period of stability for a switching frequency of 40 MHz is shorter than ${hbox {40}}~mu{hbox {s}}$.
机译:本文提出了一种新型的频率偏移技术,以提高频率合成器的工作范围,以长期用于高级演进和认知无线电应用。常规的宽带频率合成器通常具有复杂的架构,例如多个锁相环(PLL),多个压控振荡器和多个混频器,以增加工作范围。这些复杂的架构具有很高的成本和功耗。在这项研究中,所提出的技术通过仅使用一个PLL同时锁定两个混频振荡器,大大增加了频率合成器的工作范围。所提出的频率合成器是使用 $ {hbox {0.18-}} mu {hbox {m}} $ CMOS技术实现的。性能测试表明,该频率合成器可实现从50 MHz到4.8 GHz的非常宽的工作频率范围,其相位噪声低于 $-{{hbox {100 dBc / Hz}}} $ 的频率偏移为100 kHz。 40 MHz开关频率的稳定周期短于 $ {hbox {40}}〜mu {hbox {s}} $

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