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首页> 外文期刊>Microwave Theory and Techniques, IEEE Transactions on >A 0.14-${hbox {mm}}^{2}$ 1.4-mW 59.4-dB-SFDR 2.4-GHz ZigBee/WPAN Receiver Exploiting a “Split-LNTA + 50% LO” Topology in 65-nm CMOS
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A 0.14-${hbox {mm}}^{2}$ 1.4-mW 59.4-dB-SFDR 2.4-GHz ZigBee/WPAN Receiver Exploiting a “Split-LNTA + 50% LO” Topology in 65-nm CMOS

机译:一个0.14-$ {hbox {mm}} ^ {2} $ 1.4-mW 59.4-dB-SFDR 2.4GHz ZigBee / WPAN接收器在65nm CMOS中采用“ Split-LNTA + 50%LO”拓扑

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A compact low-power 2.4-GHz ZigBee/wireless personal area network receiver is reported. It optimizes passive pre-gain with an inverter-based split low-noise transconductance amplifier (split-LNTA) to avoid the RF balun and its associated insertion loss, while enabling isolated in-phase (I)/quadrature (Q) passive mixing. The latter essentially saves power as a 50%-duty-cycle local oscillator (50% LO) can be generated more efficiently than its 25% counterpart. Specifically, a 2.4-GHz LC voltage-controlled oscillator (VCO) followed by an input-impedance-boosted Type-II RC-CR network produces the desired 50% four-phase LO with optimized power, I/Q accuracy, and phase noise. We also analytically compare the proposed “split-LNTA $+$ 50% LO” architecture with the existing “single-LNTA $+$ 25% LO,” identifying their distinct features under current- and voltage-mode operations. The receiver fabricated in 65-nm CMOS exhibits 32-dB voltage gain, 8.8-dB noise figure (NF) and $-{hbox{7}} mathchar"702D {hbox{dBm}}$ out-band input-referred third-order intercept point that correspond to 59.4-dB spurious-free dynamic range. The VCO measures $- {hbox{111.4}} mathchar"702D {hbox{dBc}}$ phase noise at 3.5-MHz offset. The achieved power (1.4 mW) and area (0.14 ${hbox {mm}}^{2}$) efficiencies are favorably comparable with the state-of-the-art.
机译:报告了一种紧凑型低功耗2.4 GHz ZigBee /无线个人区域网络接收器。它利用基于逆变器的分离式低噪声跨导放大器(split-LNTA)来优化无源预增益,从而避免RF平衡-不平衡转换器及其相关的插入损耗,同时实现隔离的同相(I)/正交(Q)无源混频。后者实质上节省了功率,因为​​与25%的本地振荡器相比,可以更高效地生成50%占空比的本地振荡器(50%LO)。具体来说,一个2.4 GHz LC压控振荡器(VCO),再加上一个输入阻抗增强的II型RC-CR网络,可产生理想的50%的四相本振,并具有优化的功率,I / Q精度和相位噪声。我们还分析地比较了建议的“拆分LNTA $ + $ 50%LO”架构和现有的“单LNTA $ + $ 25%LO”架构,确定了它们在电流模式和电压模式下的独特功能。采用65 nm CMOS制成的接收器具有32 dB的电压增益,8.8 dB的噪声系数(NF)和$-{hbox {7}} mathchar“ 702D {hbox {dBm}} $带外输入参考的第三位对应于59.4 dB无杂散动态范围的阶跃截点VCO在3.5 MHz偏移处测量$-{hbox {111.4}} mathchar“ 702D {hbox {dBc}} $相位噪声。达到的功率(1.4 mW)和面积(0.14 $ {hbox {mm}} ^ {2} $)的效率可与最新技术媲美。

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