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首页> 外文期刊>Microwave Theory and Techniques, IEEE Transactions on >A Transformer-Based Poly-Phase Network for Ultra-Broadband Quadrature Signal Generation
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A Transformer-Based Poly-Phase Network for Ultra-Broadband Quadrature Signal Generation

机译:基于变压器的多相网络,用于产生超宽带正交信号

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摘要

This paper presents a transformer-based poly-phase network to generate fully differential quadrature signals with low loss, compact area, and high-precision magnitude and phase balance over an ultra-wide bandwidth. A fully differential high-coupling 8-port folded transformer-based quadrature hybrid serves as the basic building block for the poly-phase unit stage to achieve significant size reduction and low loss. Multiple poly-phase unit stages can be cascaded to form the multistage poly-phase network to substantially extend the quadrature signal generation bandwidth. The designs of the high-coupling transformer-based quadrature hybrid, the poly-phase unit stage, and the multistage transformer-based poly-phase network are presented with the closed-form design equations in this paper. As a proof-of-concept design, a 3-stage transformer-based poly-phase network is implemented in a standard 65 nm bulk CMOS process with a core area of 772 m925 m. Measurement results of this poly-phase network over 3 independent samples demonstrate that the output In-Phase and Quadrature (I/Q) magnitude mismatch is less than 1 dB from 2.8 GHz to 21.8 GHz with a passive loss of 3.65 dB at 6.4 GHz. The measured output I/Q phase error is less than 10 from 0.1 GHz to 24 GHz. The effective Image Rejection Ratio (IRR) based on the measured I/Q balancing is more than 30 dB from 3.7 GHz to 22.5 GHz. The 3-stage transformer-based poly-phase network design achieves high-quality quadrature signal generation over a first-ever one-decade bandwidth together with low-loss and compact area.
机译:本文提出了一种基于变压器的多相网络,可在超宽带宽上产生具有低损耗,紧凑型面积,高精度幅度和相位平衡的全差分正交信号。基于全差分,高耦合,8端口,折叠式变压器的正交混合电路,是多相单元级的基本构建模块,可显着减小尺寸并降低损耗。可以将多个多相单元级级联以形成多级多相网络,以充分扩展正交信号生成带宽。利用闭式设计方程,给出了基于高耦合变压器的正交混合电路,多相单元级和基于多级变压器的多相网络的设计。作为概念验证设计,在标准65 nm体CMOS工艺中实现了基于三级变压器的多相网络,其核心面积为772 m925 m。该多相网络在3个独立样本上的测量结果表明,从2.8 GHz到21.8 GHz,输出同相和正交(I / Q)幅度失配小于1 dB,在6.4 GHz时的无源损耗为3.65 dB。从0.1 GHz到24 GHz,测得的输出I / Q相位误差小于10。从3.7 GHz到22.5 GHz,基于测得的I / Q平衡的有效镜像抑制比(IRR)大于30 dB。基于三级变压器的多相网络设计可在前所未有的十年带宽上实现高质量的正交信号生成,并具有低损耗和紧凑的面积。

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