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Design of interleavers for turbo codes: iterative interleaver growth algorithms of polynomial complexity

机译:Turbo码交织器的设计:多项式复杂度的迭代交织器增长算法

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This paper addresses the problem of designing interleavers for parallel concatenated convolutional codes (PCCCs) tailored to specific constituent codes. We start by establishing the role of the interleaver in the PCCC and the various parameters that influence the performance of the PCCC with a given interleaver. Subsequently, we define a canonical form of the interleaving engine denoted as the finite-state permuter (FSP) and demonstrate the minimal delay property of this canonical form. For any given permutation, we present a procedure for deriving the canonical FSP engine. We address the issue of implementation of the FSP and propose a very simple structure for the FSP. Next, using the structural property of the FSP engine, we develop a systematic iterative technique for construction of interleavers with a complexity that is polynomial in the interleaver size. Subsequently, we develop a cost function that, coupled with the iterative interleaver growth procedure, can be used to design optimized interleavers for PCCCs. We provide examples of application of the interleaver design technique, and compare the designed interleavers with some of the interleavers of comparable size found in the literature.
机译:本文针对为特定组成码量身定制的并行级联卷积码(PCCC)设计交织器的问题。我们首先确定交织器在PCCC中的作用以及影响给定交织器PCCC性能的各种参数。随后,我们定义了交错引擎的规范形式,称为有限状态置换器(FSP),并演示了该规范形式的最小延迟特性。对于任何给定的排列,我们提供了导出规范FSP引擎的过程。我们解决了FSP的实施问题,并为FSP提出了一个非常简单的结构。接下来,利用FSP引擎的结构特性,我们开发了一种用于构造交织器的系统迭代技术,其复杂度是交织器大小的多项式。随后,我们开发了一个成本函数,再结合迭代交织器增长过程,可用于设计PCCC的优化交织器。我们提供了交织器设计技术的应用示例,并将设计的交织器与文献中发现的一些大小相当的交织器进行了比较。

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