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首页> 外文期刊>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems >A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design
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A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design

机译:一种基于网络流的倒装芯片设计RDL路由算法

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摘要

The flip-chip package gives the highest chip density of any packaging method to support the pad-limited application-specific integrated circuit designs. In this paper, we propose the first router for the flip-chip package in the literature. The router can redistribute nets from wire-bonding pads to bump pads and then route each of them. The router adopts a two-stage technique of global routing followed by detailed routing. In global routing, we use the network flow algorithm to solve the assignment problem from the wire-bonding pads to the bump pads and then create the global path for each net. The detailed routing consists of three stages, namely: 1) cross-point assignment; 2) net ordering determination; and 3) track assignment, to complete the routing. Experimental results based on seven real designs from the industry demonstrate that the router can reduce the total wirelength by 10.2%, the critical wirelength by 13.4%, and the signal skews by 13.9%, as compared with a heuristic algorithm currently used in industry.
机译:倒装芯片封装可提供所有封装方法中最高的芯片密度,以支持焊盘受限的专用集成电路设计。在本文中,我们在文献中提出了倒装芯片封装的第一个路由器。路由器可以将网络从引线键合焊盘重新分配到缓冲垫,然后对它们进行布线。路由器采用两阶段的全局路由技术,然后进行详细路由。在全局路由中,我们使用网络流算法来解决从引线键合焊盘到凸点焊盘的分配问题,然后为每个网络创建全局路径。详细的路由包括三个阶段,即:1)交叉点分配; 2)净订货确定; 3)跟踪分配,以完成路由。基于行业中七种实际设计的实验结果表明,与目前行业中使用的启发式算法相比,路由器可以将总线长减少10.2%,将临界线长减少13.4%,并将信号偏斜减少13.9%。

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