Ratioed voter circuit for testing and fault-tolerance in VLSIprocessing arrays

摘要

Fault detection and fault-tolerance in modular processing arrays are reviving the use of majority voting techniques. In this paper, a simple voting circuit structure, called a ratioed voter, is analyzed to prove its reliable operation when Dynamic N-Modular Redundant (DNMR) tuples are configured for testing in fault-tolerant processing arrays. Its application in VLSI design for self-testing would lead to low area overhead and high diagnosability, both contributing to improve yield. Moreover, the flexibility of such a structure, which allows modulation of the voting level (N), permits a common approach for fabrication-time and on-line testing