Phase-jitter dynamics of digital phase-locked loops: Part II

摘要

For pt.I see ibid., vol.46, pp.545-58 (1999). In Part I, we examined the unwanted phase jitter that occurs in digital phase-locked loops due to frequency quantization in a number-controlled oscillator. In the treatment of the second-order loop that made up the bulk of that work, we concentrated on the case of a sinusoidal input whose frequency, normalized to the quantization increment, is rational with a low denominator, but not an integer. In this paper we extend that analysis to handle all input frequencies. We will study in two-dimensional state space the dynamics of the map modeling the second order loop, and examine the location and nature of the steady-state behavior of the system. The analysis adds to the insights into digital phase locked loops produced by our previous work, and also reveals properties of interest to students of nonlinear dynamics. We will see in particular that the jitter width significantly increases close to the low-denominator rational frequencies