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A Spatial Contrast Retina With On-Chip Calibration for Neuromorphic Spike-Based AER Vision Systems

机译:基于片上校准的基于神经形态峰值的AER视觉系统的空间对比度视网膜

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We present a 32 $times$ 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57% to 6.6% (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is $58 mu{hbox {m}}times 56 mu{hbox {m}}$, while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35-$mu{hbox {m}}$ CMOS process.
机译:我们提出了一个32 x 32像素的对比度视网膜微芯片,该芯片提供其输出作为地址事件表示(AER)流。将空间对比度计算为像素光电流与使用扩散网络获得的相邻像素之间的局部平均值之比。这种基于电流的计算会在相邻像素之间产生大量的失配,因为电流可能低至几个皮安。因此,已经包含了紧凑的校准电路来修剪每个像素。测量表明,不匹配标准偏差从57%降低到6.6%(室内照明)。本文介绍了像素的设计及其空间对比度计算和校准部分。约三分之一的像素面积用于5位校准电路。像素面积为58亩乘以56亩,而在1-kHz事件发生率下,其电流消耗约为20 nA。提供了使用标准的0.35-μCMOS工艺制造的原型的广泛实验结果。

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