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首页> 外文期刊>IEEE transactions on circuits and systems . I , Regular papers >3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits
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3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits

机译:3-D nFPGA:3-D CMOS /纳米材料混合数字电路的可重配置架构

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摘要

In this paper, we introduce a novel reconfigurable architecture, named 3D field-programmable gate array (3D nFPGA), which utilizes 3D integration techniques and new nanoscale materials synergistically. The proposed architecture is based on CMOS nanohybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into CMOS fabrication process. This architecture also has built-in features for fault tolerance and heat alleviation. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4x footprint reduction comparing to the traditional CMOS-based 2D FPGAs. With a customized design automation flow, we evaluate the performance and power of 3D nFPGA driven by the 20 largest MCNC benchmarks. Results demonstrate that 3D nFPGA is able to provide a performance gain of 2.6 x with a small power overhead comparing to the traditional 2D FPGA architecture.
机译:在本文中,我们介绍了一种新颖的可重构架构,称为3D现场可编程门阵列(3D nFPGA),该架构可协同利用3D集成技术和新型纳米级材料。所提出的架构基于CMOS纳米混合技术,该技术将诸如碳纳米管束和纳米线交叉开关等纳米材料结合到CMOS制造过程中。该体系结构还具有用于容错和散热的内置功能。与传统的基于CMOS的2D FPGA相比,利用FPGA的独特功能和通过纳米材料的应用实现的新颖3D堆叠方法,3D nFPGA的占地面积减少了4倍。通过定制的设计自动化流程,我们评估了20个最大的MCNC基准测试驱动的3D nFPGA的性能和功能。结果表明,与传统的2D FPGA架构相比,3D nFPGA能够以较小的功耗开销提供2.6倍的性能增益。

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