Digital architectures for hybrid CMOS/nanodevice circuits.

摘要

This dissertation describes architectures of digital memories and reconfigurable Boolean logic circuits for the prospective hybrid CMOS/nanowire/nanodevice ("CMOL") technology. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with those of molecular-scale nanodevices. Two-terminal nanodevices would be naturally incorporated into nanowire crossbar fabric, enabling very high function density at acceptable fabrication costs. In order to overcome the CMOS/nanodevice interface problem, in CMOL circuits the interface is provided by sharp-tipped pins that are distributed all over the circuit area, on top of the CMOS stack.; The most straightforward possible application of CMOL circuits is terabit-scale "resistive" memories, in which nanodevices (e.g., single molecules) would be used as single-bit, memory cells, while the semiconductor subsystem would perform all the peripheral (input/output, coding/decoding, line driving, and sense amplification) functions. Using bad-bit exclusion and error-correcting codes synergistically we show that CMOL memories with a nano/CMOS pitch ratio close to 1/3 may overcome purely semiconductor memories in useful density if the fraction of bad nanodevices is below ∼ 15%, even for the 30 ns upper bound on the total access time. As the nanotechnology matures, and the pitch ratio approaches an order of magnitude, the CMOL memories may be far superior to the densest semiconductor memories by providing, e.g., 1 Tbit/cm2 density even for the plausible defect fraction of 2%.; Even greater defect tolerance (about 20% for 99% circuit yield) can be achieved in uniform a cell-FPGA-like CMOL circuits. In such circuits, two-terminal nanodevices provide programmable diode functionality for logic circuit operation, and allow circuit mapping and reconfiguration around defective nanodevices, while CMOS subsystem is used for signal restoration and latching. The cell-based architecture is based on a uniform CMOL fabric of "tiles", while each tile consists of 12 four-transistor basic cells and one latch cell. To evaluate the potential performance of CMOL FPGA we have developed a completely custom design automation tools. Using these tools we have successfully mapped on CMOL FPGA the well known Toronto 20 benchmark circuits and estimated their performance. The results have shown that, in addition to high defect tolerance, CMOL FPGA circuits may have extremely high density (more than two orders of magnitude higher that of usual CMOS FPGA with the same CMOS design rules) while operating at higher speed at acceptable power consumption.