Time-Mode Analog-to-Digital Conversion Using Standard Cells

摘要

Synthesizable all-digital ADCs that can be designed, verified and taped out using a digital design flow are of interest due to a consequent reduction in design cost and an improved technology portability. As a step towards high performance synthesizable ADCs built using generic and low accuracy components, an ADC designed exclusively with standard digital cell library components is presented. The proposed design is a time-mode circuit employing a VCO based multi-bit quantizer. The ADC has first order noise-shaping due to inherent error feedback of the oscillator and sinc anti-aliasing filtering due to continuous-time sampling. The proposed architecture employs a Gray-counter based quantizer design, which mitigates the problem of partial sampling of digital data in multi-bit VCO-based quantizers. Furthermore, digital correction employing polynomial-fit estimation is proposed to correct for VCO non-linearity. The design occupies 0.026 mm when fabricated in a 65 nm CMOS process and delivers an ENOB of 8.1 bits over a signal bandwidth of 25.6 MHz, while sampling at 205 MHz. The performance is comparable to that of recently reported custom designed single-ended open-loop VCO-based ADCs, while being designed exclusively with standard cells, and consuming relatively low average power of 3.3 mW achieving an FoM of 235 fJ/step.