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A Reconfigurable $DeltaSigma$ ADC With Up to 100 MHz Bandwidth Using Flash Reference Shuffling

机译:使用闪存参考混洗的带宽高达100 MHz的可重构 $ DeltaSigma $ ADC

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A reconfigurable 65-nm continuous-time low-pass delta-sigma modulator operates with a sampling frequency from 491 MHz to 1536 MHz, a signal bandwidth from 10 MHz to 100 MHz, and a dynamic range of 75.4 dB to 62.8 dB, respectively. Flash ADC calibration and reference shuffling with zipper rotation are used to improve the linearity of the flash, while also increasing the highest sampling rate and bandwidth of the modulator. Dynamic element matching using a randomized incremented pointer improves the linearity of the DAC.
机译:可重新配置的65 nm连续时间低通delta-sigma调制器的采样频率为491 MHz至1536 MHz,信号带宽为10 MHz至100 MHz,动态范围分别为75.4 dB至62.8 dB。闪存ADC校准和带有拉链旋转的基准改组用于改善闪存的线性度,同时还提高了调制器的最高采样率和带宽。使用随机递增指针进行动态元素匹配可改善DAC的线性度。

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