首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >A 1.2-V 4.2- src='/images/tex/19455.gif' alt='hbox {ppm}/^{circ}hbox {C}'> High-Order Curvature-Compensated CMOS Bandgap Reference
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A 1.2-V 4.2- src='/images/tex/19455.gif' alt='hbox {ppm}/^{circ}hbox {C}'> High-Order Curvature-Compensated CMOS Bandgap Reference

机译:一个1.2-V 4.2- src =“ / images / tex / 19455.gif” alt =“ hbox {ppm} / ^ {circ} hbox {C}”> 高阶曲率补偿CMOS带隙基准

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摘要

This study presents a high-precision CMOS bandgap reference (BGR) circuit with low supply voltage. The proposed BGR circuit consists of two BGR cores and a curvature correction circuit, which includes a current mirror and a summing circuit. Two BGR cores adopt conventional structures with the curvature-down characteristics. A current-mirror circuit is proposed to implement one of the BGR cores to have the curvature-up characteristic. Selection of the appropriate resistances in the BGR cores results in one reference voltage with a well balanced curvature-down characteristic and another reference voltage with an evenly balanced curvature-up characteristic. The summation of these reference voltages is proposed to achieve a high-order curvature compensation. This curvature correction circuit causes the proposed BGR circuit without any trimming to show a measured temperature coefficient (TC) as low as 4.2 over a wide temperature range of 160 at a power supply voltage of 1.2 V. The average TC for 8 random samples is approximately 9.3 . The measured power-supply rejection ratio (PSRR) of 30 dB is achieved at the frequency of 100 kHz. The total chip size is 0.063 with a standard 0.13- CMOS process.
机译:这项研究提出了一种具有低电源电压的高精度CMOS带隙基准(BGR)电路。提出的BGR电路由两个BGR内核和一个曲率校正电路组成,后者包括一个电流镜和一个求和电路。两个BGR磁芯采用具有曲率下降特性的常规结构。提出了一种电流镜电路,以实现BGR磁芯之一以具有向上弯曲的特性。在BGR磁芯中选择适当的电阻会导致一个基准电压具有良好的平衡的向下弯曲特性,而另一个基准电压具有均匀的平衡的向上弯曲特性。提出这些参考电压的总和以实现高阶曲率补偿。该曲率校正电路使拟议的BGR电路在没有任何修整的情况下在电源电压为1.2 V时在160的较宽温度范围内显示的测得温度系数(TC)低至4.2。8个随机样本的平均TC约为9.3。在100 kHz的频率下,测得的电源抑制比(PSRR)为30 dB。采用标准的0.13-CMOS工艺时,总芯片尺寸为0.063。

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