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首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >Degradation of Alias Rejection in Continuous-Time Delta–Sigma Modulators by Weak Loop-Filter Nonlinearities
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Degradation of Alias Rejection in Continuous-Time Delta–Sigma Modulators by Weak Loop-Filter Nonlinearities

机译:通过弱环路滤波器非线性来降低连续时间Delta-Sigma调制器中的混叠抑制

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Implicit anti-aliasing is a remarkable property of continuous-time delta–sigma modulators employing a time-invariant loop filter. It turns out that weak nonlinearity of the operational transconductance amplifier (OTA) used in the input integrator, in conjunction with the DAC pulse shape and OTA parasitics can greatly degrade the alias rejection of the modulator. The authors report and analyze this hitherto undiscovered mechanism. The theory is borne out by measurement results from a fourth-order single-bit filtering delta–sigma modulator designed in a 65-nm CMOS process. The alias-rejection of the modulator, which is expected to be about 160dB, is degraded to around 70dB by weak OTA nonlinearity and OTA parasitics.
机译:隐式抗混叠是采用时不变环路滤波器的连续时间delta-sigma调制器的显着特性。事实证明,在输入积分器中使用的运算跨导放大器(OTA)的弱非线性以及DAC脉冲形状和OTA寄生效应会大大降低调制器的混叠抑制。作者报告并分析了这一迄今未发现的机制。该理论通过采用65纳米CMOS工艺设计的四阶单比特滤波delta-sigma调制器的测量结果得到证实。由于弱的OTA非线性和OTA寄生效应,调制器的混叠抑制(预期约为160dB)会降低至70dB左右。

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