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首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications
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A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications

机译:适用于智能电源应用的完全可编程的EFPGA - 增强SoC

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This paper proposes a reconfigurable system on chip (SoC) for smart power applications. The system is composed of an ultra-low-power microcontroller for standard software programmability, coupled to an embedded-FPGA (eFPGA) to perform control-driven applications and lightweight digital signal processing, at lower power consumption and higher responsiveness than with processor-based execution. To the best of our knowledge, this is the first heterogeneous reconfigurable SoC targeting smart power applications. The SoC targets BCD technologies integrating bipolar, CMOS, and DMOS devices, typically featuring a small number of metal layers when compared with the traditional CMOS technologies. The added value of the proposed system is that the digital system is fully synthesizable since the eFPGA is based on a soft-core approach. This paper presents the results of integrating an eFPGA with a computational capability of $simeq 1ext{k}$ equivalent gates in STMicroelectronics 90-nm BCD technology featuring five metal layers and high- $k$ transistors. We benchmarked our architecture on a wide range of applications relevant to the smart power domain. eFPGA integration in SoCs introduces a 20& x0025;-27& x0025; area overhead but has a straightforward benefit in terms of energy consumption, which proves reduction from about $10imes $ to $800imes $ . In terms of latency, the eFPGA implementation allows a gain from $8imes $ to $145imes $ comparing the pure cycles count.
机译:本文提出了用于智能电力应用的芯片(SOC)的可重新配置系统。该系统由超低功耗微控制器组成,用于标准软件可编程性,耦合到嵌入式FPGA(EFPGA),以执行控制驱动的应用和轻量级数字信号处理,低功耗和比基于处理器的更高响应性更高执行。据我们所知,这是第一个异构重新配置SoC目标智能电力应用。 SOC目标BCD技术集成了双极,CMOS和DMOS设备,通常在与传统CMOS技术相比时具有少量金属层。所提出的系统的附加值是数字系统是完全合成的,因为EFPGA基于软核心方法。本文介绍了在STMicroelectronics 90-NM BCD技术中使用$ SIMEQ 1 Text {K} $等效栅极的计算能力集成了EFPGA的结果,该技术为五个金属层和高度$ k $晶体管。我们在与智能电源域相关的广泛应用程序上基准测试我们的架构。 SOC的EFPGA集成介绍了20&x0025; -27&x0025;面积开销,但能源消耗方面具有直截了当的益处,从而减少了约10美元的价格至800美元。在延迟方面,EFPGA实现允许从8美元的增益到$ 145 times $比较纯循环计数。

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