POWER CONSUMPTION MODELING AND CHARACTERIZATION OF THE C6201

摘要

THIS NEW APPROACH CHARACTERIZES POWER DISSIPATION ON COMPLEX DSPS. ITS PROCESSOR MODEL RELIES ON AN INITIAL FUNCTIONAL-LEVEL POWER ANALYSIS OF THE TARGET PROCESSOR TOGETHER WITH A CHARACTERIZATION THAT QUALIFIES THE MORE SIGNIFICANT ARCHITECTURAL AND ALGORITHMIC PARAMETERS FOR POWER DISSIPATION. THESE PARAMETERS COME FROM A SIMPLE PROFILING OF THE ASSEMBLY CODE, THIS FUNCTIONAL MODEL ACCOUNTS FOR DEEPLY PIPELINED, SUPERSCALAR, AND HIERARCHICAL MEMORY ARCHITECTURES.