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Design of fixed-point iterative decoders for concatenated codeswith interleavers

机译:带交织器的级联码定点迭代解码器的设计

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We discuss the effects of quantization on the performance of theniterative decoding algorithm of concatenated codes with interleavers.nQuantization refers here to the log-likelihood ratios coming from thensoft demodulator and to the extrinsic information passed from one stagenof the decoder to the next. We discuss the cases of a single soft-inputnsoft-output (SISO) module, in its additive log-likelihood versionn(L-SISO), performing sequentially all iterations (an implementationnsolution coping with medium-low data rate as compared with the hardwarenclock), and that of a pipelined structure in which a dedicated hardwarenis in charge of each SISO operation (an implementation suitable for highndata rates). We give design rules in both cases, and show that ansuitable rescaling of the extrinsic information yields almost idealnperformance with the same number of bits (five) representing bothnlog-likelihood ratios and extrinsic information at any decoder stage
机译:我们讨论了量化对具有交错器的级联代码的迭代解码算法的性能的影响。n量化在这里是指来自软解调器的对数似然比,以及从解码器的一个阶段传递到下一阶段的外部信息。我们讨论单个软输入n软输出(SISO)模块在其加法对数似然版本n(L-SISO)中的情况,按顺序执行所有迭代(与硬件nclock相比,解决方案具有中等低数据速率的解决方案) ,以及由专用硬件负责每个SISO操作(适合高数据速率的实现)的流水线结构。我们在两种情况下都给出了设计规则,并表明对外部信息进行适当的重新缩放可产生几乎理想的性能,同时在任何解码器阶段,相同数目的位数(五位)代表了对数似然比和外部信息

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