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Crosstalk-Aware Placement

机译:串扰感知放置

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摘要

With today's rapidly shrinking process geometries, designers must address crosstalk, electromigration, IR drop, and other effects earlier in the design cycle to achieve signal integrity. The authors present a new placement algorithm that minimizes crosstalk and increases design speed 8% on average, in comparison with a traditional timing-driven, congestion-aware placement flow. Advances in semiconductor fabrication technology, such as smaller minimum feature sizes, increased metal layers, and stacked vias, have contributed to the fast and steady enhancement of VLSI circuit performance and density for more than two decades. However, for VLSI designs in processes under 0.18 micron, electrical effects such as crosstalk, electromigration, wire self-heating, and IR drop negatively affect signal integrity, which is critical to the performance and reliability of electronic systems. Of these problems, crosstalk induced by capacitive coupling is the one back-end vendors see most often. Crosstalk typically occurs between two adjacent wires when their cross-coupling capacitance is large enough to influence one another's electrical characteristics. The two major effects of crosstalk are delays (which change signal propagation time and thus can cause setup or hold time failures) and glitches (which can cause voltage spikes on wires, resulting in false logic behavior). Researchers have proposed models for extracting RCL networks from postrouting circuits. Others have proposed optimization techniques that reduce crosstalk effects after high-coupling nets are identified. However, most optimization techniques work with a postrouting circuit, so their effectiveness is limited. For example, if the initial placement introduces many potential couplings, the router cannot fix all of them without violating design constraints. For such cases, we need new techniques that prevent signal net coupling earlier in the design cycle. Although other factors such as driver strength and transition time also affect noise, coupling capacitance dominates the peak noise computation. Here, we present a crosstalk-aware placement algorithm that reduces signal net coupling capacitance. This algorithm uses a novel probabilistic model to estimate coupling capacitance at the placement stage and controls placement density to reduce the number of highly coupled regions.
机译:随着当今工艺尺寸的迅速缩小,设计人员必须在设计周期的早期阶段解决串扰,电迁移,IR下降和其他影响,以实现信号完整性。与传统的时序驱动,拥塞感知的布局流程相比,作者提出了一种新的布局算法,该算法可最大程度地减少串扰并平均提高设计速度8%。半导体制造技术的进步,例如更小的最小特征尺寸,增加的金属层和堆叠的过孔,已经为VLSI电路性能和密度的快速稳定的提高做出了超过二十年的贡献。但是,对于采用0.18微米以下工艺的VLSI设计,诸如串扰,电迁移,导线自热和IR下降等电效应会对信号完整性产生负面影响,这对于电子系统的性能和可靠性至关重要。在这些问题中,后端耦合供应商最常看到的是电容耦合引起的串扰。当相邻的两根导线的交叉耦合电容大到足以影响彼此的电气特性时,通常会发生串扰。串扰的两个主要影响是延迟(这会改变信号传播时间,从而导致建立或保持时间失败)和毛刺(可能导致导线上的电压尖峰,从而导致错误的逻辑行为)。研究人员提出了从后路由电路中提取RCL网络的模型。其他人提出了优化技术,可在确定高耦合网络后降低串扰效应。但是,大多数优化技术都与后路由电路一起使用,因此其有效性受到限制。例如,如果初始放置引入了许多潜在的耦合,则路由器无法在不违反设计约束的情况下固定所有耦合。对于这种情况,我们需要在设计周期的早期就防止信号网耦合的新技术。尽管驱动器强度和过渡时间等其他因素也会影响噪声,但耦合电容在峰值噪声计算中占主导地位。在这里,我们提出了一种可降低信号净耦合电容的串扰感知布局算法。该算法使用新颖的概率模型来估计贴装阶段的耦合电容,并控制贴装密度以减少高度耦合区域的数量。

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