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首页> 外文期刊>IEEE computer architecture letters >An Energy-Efficient Processor Architecture for Embedded Systems
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An Energy-Efficient Processor Architecture for Embedded Systems

机译:嵌入式系统的节能处理器架构

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摘要

We present an efficient programmable architecture for compute-intensive embedded applications. The processor architecture uses instruction registers to reduce the cost of delivering instructions, and a hierarchical and distributed data register organization to deliver data. Instruction registers capture instruction reuse and locality in inexpensive storage structures that are located near to the functional units. The data register organization captures reuse and locality in different levels of the hierarchy to reduce the cost of delivering data. Exposed communication resources eliminate pipeline registers and control logic, and allow the compiler to schedule efficient instruction and data movement. The architecture keeps a significant fraction of instruction and data bandwidth local to the functional units, which reduces the cost of supplying instructions and data to large numbers of functional units. This architecture achieves an energy efficiency that is 23× greater than an embedded RISC processor.
机译:我们为计算密集型嵌入式应用提供了一种高效的可编程体系结构。处理器体系结构使用指令寄存器来减少传递指令的成本,并使用分层的分布式数据寄存器组织来传递数据。指令寄存器捕获指令重用和位于功能单元附近的廉价存储结构中的位置。数据寄存器组织捕获层次结构不同级别中的重用和本地性,以降低传递数据的成本。暴露的通信资源消除了流水线寄存器和控制逻辑,并允许编译器调度有效的指令和数据移动。该体系结构将大部分指令和数据带宽保持在功能单元本地,这降低了向大量功能单元提供指令和数据的成本。与嵌入式RISC处理器相比,该体系结构的能效提高了23倍。

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