A low-noise, low-power embedded modular SRAM is described. A 512/spl times/15 configuration at 3.3 V generates a maximum of 8.2 mAs dI/dt and consumes 0.24 mW/MHz, the lowest power dissipation ever reported for a modular embedded memory. Results are achieved using a pulsed divided word line architecture, with internal cascaded clocks, weak static sensing, low-noise buffers and flip-flops and low-noise low-power decoding techniques. Alternatives in the core cell, sense amplifier and read/write architecture designs are discussed. Circuit details, as well as experimental and simulation results, are presented.
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机译：描述了一种低噪声，低功耗的嵌入式模块化SRAM。 3.3 V时的512 / spl times / 15配置产生的最大值为8.2 mA / ns dI / dt，功耗为0.24 mW / MHz，这是模块化嵌入式存储器所报告的最低功耗。使用具有内部级联时钟，弱静态感测，低噪声缓冲器和触发器以及低噪声低功耗解码技术的脉冲划分字线架构可实现结果。讨论了核心单元，读出放大器和读/写体系结构设计中的替代方案。给出了电路细节以及实验和仿真结果。
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