Direct sequence spread spectrum (DSSS) transmissions require andespreading stage within the standard receiver block to recover thenspread spectrum signal. For long spread spectrum codes, the correlationnblock can be a large portion of the receiver size, hence a considerablenportion of the power consumption. The authors look at two powernreduction alternatives for a parallel spread spectrum correlator, bynanalysing the algorithm and designing a baseline correlator and byninvestigating how to streamline the arithmetic operations in one case,nand optimising the sample storage in the other. The two correlatorndesigns are compared with a mix of analytical techniques and simulationndata to determine the optimal correlator alternative for the DSSSnapplication. The final analysis shows that the register file basedncorrelator can reduce the power by over 30% for bus widths greater thann6 by using a structure which maintains the multi-bit data samples in anstatic area and by rotating the single bit coefficients around the datanwith a circular shift register
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