Circuit partitioning algorithm for low-power design under areaconstraints using simulated annealing

摘要

A synthesis algorithm is proposed for the design of low-powerncombinational circuits under area constraints. The algorithm partitionsna given circuit into several subcircuits such that only a selectednsubcircuit is activated at a time, hence reducing unnecessary signalntransitions. Partitioning is performed through an adaptive simulatednannealing algorithm, employing a cost function modelled for low-powernconsumption under given area constraints. Experiments have beennperformed for the MCNC benchmark circuits using the power analysisnpackage provided in the the Synopsys Design Analyzer. Results show thatnthe proposed algorithm generates circuits which consume less power thannthose by the area-optimisation package in Synopsys Design Analyzer andnprecomputation algorithm