Novel PLL-based frequency synthesiser without using the frequencydivider

摘要

A technique of implementing a PLL-based frequency synthesiser (FS)nwithout using the frequency divider sub-circuit has been discussed. Tongenerate the loop oscillator control signal, proportional to the phasenmismatch between the reference signal and the synthesised signal (wherenthe frequency of the latter is a multiple of that of the former), thenproposed structure uses a phase detector used in data clock recoveryncircuits with some modification. The operating conditions of thenproposed system have been analytically examined and the results of anprototype hardware experiment carried out around 500 kHz are given. Thenstudy confirms the possibility of designing a dividerless indirect FSnwith low power consumption and high spectral purity