The authors propose an efficient path balancing algorithm tonreduce glitch power dissipation in CMOS logic circuits. The proposednalgorithm employs gate sizing and buffer insertion methods to achievenpath balancing. The gate sizing technique reduces not only glitches, butnalso the effective capacitance in the circuit. For the paths whichnremain unbalanced after gate sizing due to the limitation of gate size,nbuffer insertion is performed. Since the buffer itself consumes power,nit is inserted between the gates where power reduction achieved bynglitch reduction is larger than the power consumed by the insertednbuffer. Determining the location of the inserted buffer is a difficultnproblem, because the power reduction achieved by an inserted buffer isnclosely related to the locations of the other inserted buffers. The ILPn(integer linear program) has been employed to determine the locations ofninserted buffers. The proposed algorithm has been tested on LGSSynth91nbenchmark circuits. Experimental results show that 61.5% of glitchnreduction and 30.4% of power reduction are achieved without increasingnthe critical path delay
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