Hardware performance analysis of the SHACAL-2 encryption algorithm

摘要

A hardware performance analysis of the SHACAL-2 encryption algorithm is presented. SHACAL-2 was one of four private-key algorithms chosen in the New European Schemes for Signatures, Integrity and Encryption (NESSIE) initiative. To the author's knowledge, there has been no previous published research work conducted on hardware SHACAL-2 architectures. Consequently, in this paper, both iterative and pipelined designs are developed and implemented. A fully pipelined encryption SHACAL-2 architecture implemented on a Virtex-II XC2V4000 device achieves a throughput of over 25 Gbit/s. This is one of the fastest encryption algorithm implementations currently available. The iterative encryption architecture operates at 432 Mbit/s on the XC2V500 device. A comparison is provided between SHACAL-2 hardware designs that incorporate carry save adders and designs that include typical full adders. The SHACAL-2 decryption algorithm is also clearly defined in the paper as it was not provided in the NESSIE submission.