Enhancing behavioural-level design flows with statistical power estimation capabilities

摘要

Power estimation of behavioural hardware descriptions is a difficult task, as it entails inferring the hardware architecture on which the behavioural specification will be mapped through synthesis before the synthesis is actually performed. To cope with the uncertainties related to handling behavioural descriptions, the concept of statistical estimation is introduced and how a prototype statistical power estimator has been implemented within a high-level design exploration framework (the AspeCts environment) is presented. The experimental results, obtained on a set of C benchmarks, have shown the feasibility of the proposed approach, both in terms of the accuracy of the power estimates and of the reduction of the execution times.